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18-mbit (512k x 36/1m x 18) pipelined sram with nobl? architecture cy7c1370dv25 CY7C1372DV25 preliminary cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05558 rev. *a revised november 9, 2004 features ? pin-compatible and functionally equivalent to zbt? ? supports 250-mhz bus operations with zero wait states ? available speed grades are 250, 200, and 167 mhz ? internally self-time d output buffer cont rol to eliminate the need to use asynchronous oe ? fully registered (inputs and outputs) for pipelined operation ? byte write capability ? single 2.5v power supply ? 2.5v i/o power supply ? fast clock-to-output times ? 2.6 ns (for 250-mhz device) ? 3.0 ns (for 200-mhz device) ? 3.4 ns (for 167-mhz device) ? clock enable (cen ) pin to suspend operation ? synchronous self-timed writes ? available in lead-free 100 tqfp, 119 bga, and 165 fbga packages ? ieee 1149.1 jtag boundary scan ? burst capability?linear or interleaved burst order ? ?zz? sleep mode option and stop clock option functional description the cy7c1370dv25 and CY7C1372DV25 are 2.5v, 512k x 36 and 1 mbit x 18 synchronous pipelined burst srams with no bus latency? (nobl ?) logic, respectively. they are designed to support unlimited true back-to-back read/write operations with no wait states. the cy7c1370dv25 and CY7C1372DV25 are equipped with the advanced (nobl) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the thr oughput of data in systems that require frequent write/read transitions. the cy7c1370dv25 and CY7C1372DV25 are pin-compatible and functionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by t he rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. write operations are controlled by the byte write selects (bw a ?bw d for cy7c1370dv25 and bw a ?bw b for CY7C1372DV25) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state co ntrol. in order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e clk c en write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s logic block diagram-cy7c1370dv25 (512k x 36)
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 2 of 30 a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk c en write drivers zz sleep control logic block diagram-CY7C1372DV25 (1m x 18) selection guide cy7c1370dv25-250 CY7C1372DV25-250 cy7c1370dv25-200 CY7C1372DV25-200 cy7c1370dv25-167 CY7C1372DV25-167 unit maximum access time 2.6 3.0 3.4 ns maximum operating current 350 300 275 ma maximum cmos standby current 70 70 70 ma shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s.
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 3 of 30 pin configurations a a a a a 1 a 0 v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz cy7c1370dv25 100-pin tqfp packages a a a a a 1 a 0 v ss v dd a a a a a a a nc nc v ddq v ss nc dqp a dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb v dd v ss dqb dqb v ddq v ss dqb dqb dqpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode CY7C1372DV25 bw d mode bw c dqc dqc dqc dqc dqpc dqd dqd dqd dqpb dqb dqa dqa dqa dqa dqpa dqb dqb (512k 36) (1m 18) bw b nc nc nc dqc nc e(288) e(144) e(72) e(36) e(288) e(144) e(72) e(36) dqpd a a
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 4 of 30 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u dq a v ddq nc nc dq c dq d dq c dq d aa aa av ddq ce 2 a v ddq v ddq v ddq v ddq nc nc a dq c dq c dq d dq d tms v dd a e(72) dqp d a a adv/ld ace 3 nc v dd aanc v ss v ss nc dqp b dq b dq b dq a dq b dq b dq a dq a nc tdi tdo v ddq tck v ss v ss v ss nc v ss v ss v ss v ss mode ce 1 v ss oe v ss v ddq bw c a v ss we v ddq v dd nc v dd v ss clk nc bw a cen v ss v ddq v ss zz nc a a a1 a0 v ss v dd nc cy7c1370dv25 (512k 36) ? bga dqp c dq b ae(36) dq c dq b dq c dq c dq c dq b dq b dq a dq a dq a dq a dqp a dq d dq d dq d dq d bw d 119-ball bga pinout bw b 234567 1 a b c d e f g h j k l m n p r t u e(36) dq a v ddq nc nc nc dq b dq b dq b dq b aa aa av ddq ce 2 a nc v ddq nc v ddq v ddq v ddq nc nc nc e(72) a dq b dq b dq b dq b nc nc nc nc tms v dd a a dqp b a a adv/ld a ce 3 nc v dd aanc v ss v ss nc nc dqp a dq a dq a dq a dq a dq a dq a dq a nc tdi tdo v ddq tck v ss v ss v ss nc v ss nc v ss v ss v ss mode ce 1 v ss nc oe v ss v ddq bw b ancnc v ss we nc v ddq v dd nc v dd nc v ss clk nc nc bw a cen v ss nc v ddq v ss nc zz nc a a a a1 a0 v ss nc v dd nc CY7C1372DV25 (1m x 18) ? bga
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 5 of 30 pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r tdo e(288) nc dqp c dq c dqp d nc dq d a ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d e(36) e(72) v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 nc a a adv/ld nc oe a a e(144) v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a 234 567 1 a b c d e f g h j k l m n p r tdo e(288) nc nc nc dqp b nc dq b a ce 1 nc ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc e(36) e(72) v ddq nc bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 nc a a adv/ld a oe a a e(144) v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a CY7C1372DV25 (1m 18) ? fbga cy7c1370dv25 (512k 36) ? fbga 165-ball fbga pinout
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 6 of 30 pin definitions pin name i/o type pin description a0 a1 a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a bw b bw c bw d input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, t he i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are thr ee-stated, and act as input data pins. oe is masked during the data portion of a write sequence, du ring the first clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend th e previous cycle when required. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [17:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq d are placed in a three-stat e condition. the outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the de vice is deselected, rega rdless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq s . during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d . mode input strap pin mode input . selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode will default high, to an interleaved burst order. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. tms test mode select synchronous this pin controls the test access port state machine . sampled on the rising edge of tck. tck jtag-clock clock input to th e jtag circuitry . v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry .
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 7 of 30 introduction functional overview the cy7c1370dv25 and CY7C1372DV25 are synchronous-pipelined burst nobl srams designed specifi- cally to eliminate wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 2.6 ns (250-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw x can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the ou tput register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent oper ation (read/write/deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. burst read accesses the cy7c1370dv25 and CY7C1372DV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequ ence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap around when incremented suffi- ciently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1370dv25 and dq a,b /dqp a,b for CY7C1372DV25). in addition, the address for the subse- quent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). on the next clock rise the data presented to dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1370dv25 & dq a,b /dqp a,b for CY7C1372DV25) (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the writ e operation is controlled by bw (bw a,b,c,d for cy7c1370dv25 and bw a,b for CY7C1372DV25) signals. the cy7c1370dv25/CY7C1372DV25 provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bw ) input will selectively write to only the desired bytes. bytes not select ed during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly v ss ground ground for the device . should be connected to ground of the system. nc ? no connects . this pin is not connected to the die. e(36,72, 144, 288) ? these pins are not connected . they will be used for expansion to the 36m, 72m, 144m and 288m densities. zz input- asynchronous zz ?sleep? input . this active high input places the devic e in a non-time critical ?sleep? condition with data integrity preserved. during normal op eration, this pin can be connected to v ss or left floating. pin definitions (continued) pin name i/o type pin description
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 8 of 30 simplify read/modify/write seq uences, which can be reduced to simple byte write operations. because the cy7c1370dv25 and CY7C1372DV25 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1370dv25 and dq a,b /dqp a,b for CY7C1372DV25) inputs. doing so will three-state the output drivers. as a safety precaution, dq and dqp (dq a,b,c,d / dqp a,b,c,d for cy7c1370dv25 and dq a,b /dqp a,b for CY7C1372DV25) are automatically three-stated during the data portion of a wr ite cycle, regardless of the state of oe . burst write accesses the cy7c1370dv25/CY7C1372DV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial addr ess, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incre- mented. the correct bw (bw a,b,c,d for cy7c1370dv25 and bw a,b for CY7C1372DV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address second address third address fourth address a1,a0 a1,a0 a1,a0 a1,a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address second address third address fourth address a1,a0 a1,a0 a1,a0 a1,a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 80 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ns
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 9 of 30 notes: 1. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are as serted, see write cycle description table for details. 2. write is defined by we and bw x . see write cycle description table for details. 3. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 4. the dq and dqp pins are controlled by the current cycle and the oe signal. 5. cen = h inserts wait states. 6. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles.during a read cycle dq s and dqp x = three-state when oe is inactive or when the device is deselected, and dq s = data when oe is active. 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active. truth table [1, 2, 3, 4, 5, 6, 7] operation address used ce zz adv/ld we bw x oe cen clk dq deselect cycle none h l l x x x l l-h three-state continue deselect cycle none x l h x x x l l-h three-state read cycle (begin burst) exte rnal l l l h x l l l-h data out (q) read cycle (continue burst) next x l h x x l l l-h data out (q) nop/dummy read (begin burst) external l l l h x h l l-h three-state dummy read (continue burst) next x l h x x h l l-h three-state write cycle (begin burst) external l l l l l x l l-h data in (d) write cycle (continue burst) next x l h x l x l l-h data in (d) nop/write abort (begin burst) none l l l l h x l l-h three-state write abort (continue burst) next x l h x h x l l-h three-state ignore clock edge (stall) current x l x x x x h l-h ? sleep mode none x h x x x x x x three-state
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 10 of 30 ieee 1149.1 serial boundary scan (jtag) the cy7c1370dv25/cy7c1372dv 25 incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this part operates in accordance with ieee standar d 1149.1-1900, but doesn?t have the set of functions required for full 1149.1 compliance. these functions fr om the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standar d 2.5v i/o logic levels. the cy7c1370dv25/CY7C1372DV25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. partial write cycle description [1, 2, 3, 8] function (cy7c1370dv25) we bw d bw c bw b bw a read h x x x x write ? no bytes written l h h h h write byte a ? (dq a and dqp a ) lhhhl write byte b ? (dq b and dqp b )lhhlh write bytes b, a l h h l l write byte c ? (dq c and dqp c )lhlhh write bytes c, a l h l h l write bytes c, b l h l l h write bytes c, b, a l h l l l write byte d ? (dq d and dqp d )llhhh write bytes d, a l l h h l write bytes d, b llhlh write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes l l l l l function (CY7C1372DV25) we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 11 of 30 tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any register. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machi ne. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the boa rd-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram i/o ring when the tap co ntroller is in the capture-dr test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 12 of 30 state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it per forms a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the in- struction register and the tap c ontroller is in the capture-dr state, a snapshot of data on th e inputs and output pins is cap- tured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap ma y then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 13 of 30 tap timing tap ac switching characteristics over the operating range [9, 10] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 25 ns t tl tck clock low time 25 ns output times t tdov tck clock low to tdo valid 5 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 9. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns. t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 14 of 30 2.5v tap ac test conditions input pulse levels ............................................... .v ss to 2.5v input rise and fall time........... .......................................... 1 ns input timing referenc e levels .........................................1.25v output reference levels.................................................1.25v test load termination supply vo ltage.............................1.25v 2.5v tap ac output load equivalent note: 11.all voltages referenced to v ss (gnd). t do 1.25v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < ta < +70c; v dd = 2.5v 0.125v unless otherwise noted) [11] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a, v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma, v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 15 of 30 identification register definitions instruction field cy7c1370dv25 CY7C1372DV25 description revision number (31:29) 000 000 reserved for version number. cypress device id (28:12) 01011001000100101 01011001000010101 reserved for future use. cypress jedec id (11:1) 00000110100 00 000110100 allows unique identification of sram vendor. id register presence (0) 1 1 indicate the presence of an id register. scan register sizes register name bit size (x18) bit size (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan order (119-ball bga package) 85 85 boundary scan order (165-ball fbga package) 89 89 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id co de and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and td o. this operation does not affect sram operations.
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 16 of 30 119-ball bga boundary scan [12, 13] cy7c1370dv25 (1m x 36) cy7c1370dv25 (1m x 36) bit # ball id bit # ball id bit # ball id 1 h4 37 b6 73 n2 2t438d4 74p2 3t539b4 75r3 4 t640f4 76t1 5 r541m4 77r1 6l542a5 78t2 7r643k4 79l3 8 u644e4 80r2 9r745g4 81t3 10 t7 46 a4 82 l4 11 p6 47 g3 83 n4 12 n7 48 c3 84 p4 13 m6 49 b2 85 internal 14 l7 50 b3 15 k6 51 a3 16 p7 52 c2 17 n6 53 a2 18 l6 54 b1 19 k7 55 c1 20 j5 56 d2 21 h6 57 e1 22 g7 58 f2 23 f6 59 g1 24 e7 60 h2 25 d7 61 d1 26 h7 62 e2 27 g6 63 g2 28 e6 64 h1 29 d6 65 j3 30 c7 66 2k 31 b7 67 l1 32 c6 68 m2 33 a6 69 n1 34 c5 70 p1 35 b5 71 k1 36 g5 72 l2 notes: 12. balls which are nc (no connect) are pre-set low 13. bit# 85 is pre-set high
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 17 of 30 119-ball bga boundary scan order [12, 13] CY7C1372DV25 (2m x 18) CY7C1372DV25 (2m x 18) bit # ball id bit # ball id bit # ball id 1 h4 37 b6 73 n2 2t438d4 74p2 3t539b4 75r3 4 t640f4 76t1 5 r541m4 77r1 6l542a5 78t2 7r643k4 79l3 8 u644e4 80r2 9r745g4 81t3 10 t7 46 a4 82 l4 11 p6 47 g3 83 n4 12 n7 48 c3 84 p4 13 m6 49 b2 85 internal 14 l7 50 b3 15 k6 51 a3 16 p7 52 c2 17 n6 53 a2 18 l6 54 b1 19 k7 55 c1 20 j5 56 d2 21 h6 57 e1 22 g7 58 f2 23 f6 59 g1 24 e7 60 h2 25 d7 61 d1 26 h7 62 e2 27 g6 63 g2 28 e6 64 h1 29 d6 65 j3 30 c7 66 2k 31 b7 67 l1 32 c6 68 m2 33 a6 69 n1 34 c5 70 p1 35 b5 71 k1 36 g5 72 l2
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 18 of 30 165-ball fbga boundary scan order [12, 14] cy7c1370dv25 (1m x 36) cy7c1370dv25 (1m x 36) bit # ball id bit # ball id bit # ball id 1 n637a9 73k2 2n738b9 74l2 3 10n 39 c10 75 m2 4 p11 40 a8 76 n1 5 p841b8 77n2 6 r842a7 78p1 7 r943b7 79r1 8 p944b6 80r2 9 p10 45 a6 81 p3 10 r10 46 b5 82 r3 11r1147a5 83p2 12 h11 48 a4 84 r4 13n1149b4 85p4 14 m11 50 b3 86 n5 15l1151a3 87p6 16 k11 52 a2 88 r6 17 j11 53 b2 89 internal 18 m10 54 c2 19 l10 55 b1 20 k10 56 a1 21 j10 57 c1 22 h9 58 d1 23 h10 59 e1 24 g11 60 f1 25 f11 61 g1 26 e11 62 d2 27 d11 63 e2 28 g10 64 f2 29 f10 65 g2 30 e10 66 h1 31 d10 67 h3 32 c11 68 j1 33 a11 69 k1 34 b11 70 l1 35 a10 71 m1 36 b10 72 j2 note: 14. bit# 89 is pre-set high
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 19 of 30 165-ball fbga boundary scan order [12, 14] CY7C1372DV25 (2m x 18) CY7C1372DV25 (2m x 18) bit # ball id bit # ball id bit # ball id 1 n637a9 73k2 2n738b9 74l2 3 10n 39 c10 75 m2 4 p11 40 a8 76 n1 5 p841b8 77n2 6 r842a7 78p1 7 r943b7 79r1 8 p944b6 80r2 9 p10 45 a6 81 p3 10 r10 46 b5 82 r3 11r1147a5 83p2 12 h11 48 a4 84 r4 13n1149b4 85p4 14 m11 50 b3 86 n5 15l1151a3 87p6 16 k11 52 a2 88 r6 17 j11 53 b2 89 internal 18 m10 54 c2 19 l10 55 b1 20 k10 56 a1 21 j10 57 c1 22 h9 58 d1 23 h10 59 e1 24 g11 60 f1 25 f11 61 g1 26 e11 62 d2 27 d11 63 e2 28 g10 64 f2 29 f10 65 g2 30 e10 66 h1 31 d10 67 h3 32 c11 68 j1 33 a11 69 k1 34 b11 70 l1 35 a10 71 m1 36 b10 72 j2
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 20 of 30 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +3.6v dc to outputs in tri-state ................... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd / v ddq commercial 0c to +70c 2.5v + _5% industrial ?40c to +85c electrical characteristics over the operating range [15, 16] parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v dd = min., i oh = ? 1.0 ma 2.0 v v ol output low voltage v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage [17] v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [17] v ddq = 2.5v ?0.3 0.7 v i x input load gnd v i v ddq ?5 5 a input current of mode input = v ss ?5 a input = v dd 30 a input current of zz input = v ss ?30 a input = v dd 5 a i oz output leakage current gnd v i v dd, output disabled ?5 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 350 ma 5.0-ns cycle, 200 mhz 300 ma 6.0-ns cycle, 167 mhz 275 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 160 ma 5.0-ns cycle, 200 mhz 150 ma 6.0-ns cycle, 167 mhz 140 ma i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 70 ma i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 135 ma 5.0-ns cycle, 200 mhz 130 ma 6.0-ns cycle, 167 mhz 125 ma i sb4 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 all speed grades 80 ma shaded areas contain advance information. notes: 15. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac)> ?2v (pulse width less than t cyc /2). 16. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 17. tested initially and after any design or process change that may affect these parameters.
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 21 of 30 capacitance [17] parameter description test conditions tqfp package bga package fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5v. v ddq = 2.5v 5 8 9 pf c clk clock input capacitance 5 8 9 pf c i/o input/output capacitance 5 8 9 pf thermal resistance [17] parameter description test conditions tqfp package bga package fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 31 45 46 c/w jc thermal resistance (junction to case) 673 c/w output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v i/o test load ac test loads and waveforms
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 22 of 30 switching characteristics over the operating range [22, 23] parameter description -250 -200 -167 unit min. max. min. max. min. max. t power [18] v cc (typical) to the first access read or write 1 1 1 ms clock t cyc clock cycle time 4.0 5 6 ns f max maximum operating frequency 250 200 167 mhz t ch clock high 1.7 2.0 2.2 ns t cl clock low 1.7 2.0 2.2 ns output times t co data output valid after clk rise 2.6 3.0 3.4 ns t eov oe low to output valid 2.6 3.0 3.4 ns t doh data output hold after clk rise 1.0 1.3 1.3 ns t chz clock to high-z [19, 20, 21] 2.6 3.0 3.4 ns t clz clock to low-z [19, 20, 21] 1.0 1.3 1.3 ns t eohz oe high to output high-z [19, 20, 21] 2.6 3.0 3.4 ns t eolz oe low to output low-z [19, 20, 21] 0 0 0 ns set-up times t as address set-up before clk rise 1.2 1.4 1.5 ns t ds data input set-up before clk rise 1.2 1.4 1.5 ns t cens cen set-up before clk rise 1.2 1.4 1.5 ns t wes we , bw x set-up before clk rise 1.2 1.4 1.5 ns t als adv/ld set-up before clk rise 1.2 1.4 1.5 ns t ces chip select set-up 1.2 1.4 1.5 ns hold times t ah address hold after clk rise 0.3 0.4 0.5 ns t dh data input hold after clk rise 0.3 0.4 0.5 ns t cenh cen hold after clk rise 0.3 0.4 0.5 ns t weh we , bw x hold after clk rise 0.3 0.4 0.5 ns t alh adv/ld hold after clk rise 0.3 0.4 0.5 ns t ceh chip select hold after clk rise 0.3 0.4 0.5 ns shaded areas contain advance information. notes: 18. this part has a voltage regulator internally; t power is the time power needs to be supplied above v dd minimum initially, before a read or write operation can be initiated. 19. t chz , t clz , t eolz , and t eohz are specified with ac test conditions shown in (b) of ac test loads. transition is meas ured 200 mv from steady-state voltage . 20. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention c ondition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 21. this parameter is sampled and not 100% tested. 22. timing reference 1.25v when v ddq = 2.5v. 23. test conditions shown in (a) of ac test loads unless otherwise noted.
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 23 of 30 switching waveforms read/write/timing [24, 25, 26] notes: 24. for this waveform zz is tied low. 25. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 26. order of the burst sequence is determined by the status of th e mode (0 = linear, 1 = interleaved). burst operations are opti onal. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data i n-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh don?t care undefined q(a6) q(a4+1)
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 24 of 30 notes: 27. the ignore clock edge or stall cycle (clock 3) illustrated cen being used to create a pause. a write is not performed during this cycle 28. device must be deselected when entering zz mode. see cycle descr iption table for all possible signal conditions to deselect the device. 29. i/os are in high-z when exiting zz sleep mode. nop,stall and deselect cycles [24, 25, 27] zz mode timing [28, 29] switching waveforms (continued) read q(a3) 456 78910 clk ce we cen bwx adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a2 d(a1) q(a2) q(a3) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 25 of 30 ordering information speed (mhz) ordering code package name package type operating range 250 cy7c1370dv25-250axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4 mm) commercial CY7C1372DV25-250axc cy7c1370dv25-250bgc bg119 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-250bgc cy7c1370dv25-250bzc bb165d 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-250bzc cy7c1370dv25-250bgxc bg119 lead-free 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-250bgxc cy7c1370dv25-250bzxc bb165d lead-free 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-250bzxc 200 cy7c1370dv25-200axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4 mm) CY7C1372DV25-200axc cy7c1370dv25-200bgc bg119 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-200bgc cy7c1370dv25-200bzc bb165d 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-200bzc cy7c1370dv25-200bgxc bg119 lead-free 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-200bgxc cy7c1370dv25-200bzxc bb165d lead-free 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-200bzxc 167 cy7c1370dv25-167axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4 mm) CY7C1372DV25-167axc cy7c1370dv25-167bgc bg119 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-167bgc cy7c1370dv25-167bzc bb165d 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-167bzc cy7c1370dv25-167bgxc bg119 lead-free 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-167bgxc cy7c1370dv25-167bzxc bb165d lead-free 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-167bzxc
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 26 of 30 250 cy7c1370dv25-250axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4 mm) industrial CY7C1372DV25-250axi cy7c1370dv25-250bgi bg119 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-250bgi cy7c1370dv25-250bzi bb165d 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-250bzi cy7c1370dv25-250bgxi bg119 lead-free 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-250bgxi cy7c1370dv25-250bzxi bb165d lead-free 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-250bzxi 200 cy7c1370dv25-200axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4 mm) CY7C1372DV25-200axi cy7c1370dv25-200bgi bg119 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-200bgi cy7c1370dv25-200bzi bb165d 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-200bzi cy7c1370dv25-200bgxi bg119 lead-free 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-200bgxi cy7c1370dv25-200bzxi bb165d lead-free 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-200bzxi 167 cy7c1370dv25-167axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4 mm) CY7C1372DV25-167axi cy7c1370dv25-167bgi bg119 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-167bgi cy7c1370dv25-167bzi bb165d 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-167bzi cy7c1370dv25-167bgxi bg119 lead-free 119-ball ball grid array (14 x 22 x 2.4 mm) CY7C1372DV25-167bgxi cy7c1370dv25-167bzxi bb165d lead-free 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) CY7C1372DV25-167bzxi shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s. lead-free bg packages(ordering code: bgx) will be available in 2005. ordering information (continued) speed (mhz) ordering code package name package type operating range
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 27 of 30 package diagrams dimensions are in millimeters. 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r0.08min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 28 of 30 package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 29 of 30 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagrams (continued) 51-85180-** 165 fbga 13 x 15 x 1.40 mm bb165d
cy7c1370dv25 CY7C1372DV25 preliminary document #: 38-05558 rev. *a page 30 of 30 document history page document title: cy7c1370dv25/CY7C1372DV25 18-mbit (512k x 36/1m x 18) pipelined sram with nobl? architecture (preliminary) document number: 38-05558 rev. ecn no. issue date orig. of change description of change ** 254509 see ecn rkf new data sheet *a 288531 see ecn syt edited descri ption under ?ieee 1149 .1 serial boundary scan (jtag)? for non-compliance with 1149.1 removed 225 mhz speed bin added lead-free information for 100-pin tqfp, 119 bga and 165 fbga package added comment of ?lead-free bg pack ages availability? below the ordering information

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